ds06-20210-2e fujitsu semiconductor data sheet semicustom cmos standard cell CS101 series description CS101 series, a 90 nm standard cell product, is a cmos asic that satisfies user?s demands for lower power consumption and higher speed. the leaka ge current of the transistors is the minimum level in the industry. three types of core transistors with a different threshol d voltage can be mixed according to user application. the design rules match industry standards, and a wi de range of ip macros are available for use. as well as providing a maximum of 100 million gates, appr oximately twice the level of integration achieved in previous products, the power consumption per gate is also reduced by about half to 2.7 nw. also, using the high- speed library increases the speed by a factor of appr oximately 1.3, with a ga te delay time of 12 ps. features technology : 90 nm si gate cmos 7- to 10-metal layers. low-k (low permittivity) material is used for all dielectric inter-layers. three different types of core transistors (low leak, standard, and high speed) can be used on the same chip. the design rules comply with industry standard processes. power supply voltage : + 1.2 v 0.1 v (standard) operation junction temperature : ? 40 c to + 125 c (standard) gate delay time : tpd = 12 ps (1.2 v, inverter, f/o = 1) gate power consumption : pd = 2.7 nw/mhz/bc (1.2 v, 2 nand, f/o = 1) high level of integration : up to 91 million gates reduced chip sized realized by i/o with pad. support for a wide range of cell sets (from low power versions to ultra high speed versions). compliance with industry standard design rules enables non-fujitsu commer cial macros to be easily incorpo- rated. compiled cell (ram, rom, others) support for ultra high speed (up to 10 gbps) interface macros. special interfaces (lvds, sstl2, etc.) supports use of industry standard libraries (.lib). uses industry standard tools and supports the optimum tools for the application. (continued)
CS101 series 2 (continued) short-term development using a physical prototyping tool one pass design using a physical synthesis tool hierarchical design environment for supporting large-scale circuits support for signal integrity, emi noise reduction support for static timing sign-off optimum package range : fbga, fc-bga, pbga,tebga macro libraries (including those in preparation) 1. logic cells (about 400 types) library sets having three different types of core tr ansistors with a different threshold value are provided. 2. ip macros compliance with the design rules recommended by th e industry standard starc (semiconductor technology academic research center) recommendations which means a wide range of commercially available ip macros can be used. fujitsu plans to offer the following macros. 3. special i/o interface macro ? adder ? and ? and-or ? and-or inverter ? buffer ? clock buffer ? decoder ? delay buffer ? enor ? eor ? inverter ? latch ? nand ? nor ? or ? or-and ? or-and inverter ? scan flip flop ? non-scan flip flop ? selector ? others cpu/dsp arm9 dsps for communications, av, and similar applications, others multi-media processing macro jpeg, mpeg, others mixed signal macro adc, dac, opamp, others compiled macro ram (1-port, 2-port), rom, product sum calculator, others pll analog pll interface macro lvds, sstl2, hstl, gtl, others fast i/f macro 6 gbps i/f, 10 gbps i/f, others
CS101 series 3 compiled cell compiled cells are macro cells which are automatically ge nerated with the bit/word configuration specified. the CS101 series has the following types of compiled cells. (note that each macro is different in word/bit range depending on the column type.) 1. clock synchronous single-port ram (1 address : 1 read/write) 2. clock synchronous dual port ram (2 address : 2 read/write) 3. clock synchronous rom 4. clock synchronous register file (2 address : 1 read, 1 write) 5. clock synchronous register file (4 address : 2 read, 2 write) large capacity memory clock synchronous single-port ram (1 address : 1 read/write) column type memory capacity (bit) word range (word) bit range (bit) 4 16 to 144 k 16 to 1 k 1 to 144 8 32 to 576 k 32 to 8 k 1 to 72 16 64 to 576 k 64 to 16 k 1 to 36 column type (bit) memory capacity (bit) word range (word) bit range (bit) 4 16 to 144 k 8 to 1 k 2 to 144 16 64 to 144 k 32 to 4 k 2 to 36 column type memory capacity (bit) word range (word) bit range (bit) 16 256 to 4 m 128 to 16 k 2 to 256 64 1 k to 4 m 512 to 64 k 2 to 64 column type memory capacity (bit) word range (word) bit range (bit) 1 8 to 18 k 4 to 128 2 to 144 column type memory capacity (bit) word range (word) bit range (bit) 1 8 to 18 k 4 to 128 2 to 144 column type memory capacity (bit) word range (word) bit range (bit) 16 64 k to 9 m 8 k to 64 k 8 to 144
CS101 series 4 absolute maximum ratings *1 : the values vary depending on the type of macros. *2 : maximum power supply current that can steadily flow. *3 : maximum output current that can steadily flow. *4 : contact your fujitsu representative for details. note : vss = 0 v warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol application rating unit min max power supply voltage vdd vddi (internal) ? 0.5 + 1.8 v vdde (external 2.5 v) ? 0.5 + 3.6 v vdde (external 3.3 v) ? 0.5 + 4.6 v input voltage * 1 vi 1.2 v ? 0.5 vddi + 0.5 ( 1.8) v 2.5 v ? 0.5 vdde + 0.5 ( 3.6) v 3.3 v ? 0.5 vdde + 0.5 ( 4.6) v output voltage vo 1.2 v ? 0.5 vddi + 0.5 ( 1.8) v 2.5 v ? 0.5 vdde + 0.5 ( 3.6) v 3.3 v ? 0.5 vdde + 0.5 ( 4.6) v storage temperature tstg plastic package ? 55 + 125 c operation junction temperature tj ?? 40 + 125 c power supply pin current * 2 id per vdd, vddi, vdde vss pin ? *4 ma output current * 3 io ?? *4 ma
CS101 series 5 recommended operating conditions ? single power supply (vdd = 1.2 v 0.1 v) (vss = 0 v) ? dual power supply (vdde = 2.5 v 0.2 v, vddi = 1.2 v 0.1 v) (vss = 0 v) ? dual power supply (vdde = 3.3 v 0.3 v, vddi = 1.2 v 0.1 v) (vss = 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min typ max power supply voltage vdd 1.1 1.2 1.3 v h level input voltage vih vdd 0.7 ? vdd + 0.3 v l level input voltage vil ? 0.3 ? vdd 0.3 v operation junction temperature tj ? 40 ?+ 125 c parameter symbol value unit min typ max power supply voltage 2.5 v vdde 2.3 2.5 2.7 v 1.2 v vddi 1.1 1.2 1.3 v h level input voltage 2.5 v cmos level vih 1.7 ? vdde + 0.3 v 1.2 v cmos level vddi 0.7 ? vddi + 0.3 v l level input voltage 2.5 v cmos level vil ? 0.3 ? + 0.7 v 1.2 v cmos level ? 0.3 ? vddi 0.3 v operation junction temperature tj ? 40 ?+ 125 c parameter symbol value unit min typ max power supply voltage 3.3 v vdde 3.0 3.3 3.6 v 1.2 v vddi 1.1 1.2 1.3 v h level input voltage 3.3 v cmos level vih 2.0 ? vdde + 0.3 v 1.2 v cmos level vddi 0.7 ? vddi + 0.3 v l level input voltage 3.3 v cmos level vil ? 0.3 ? + 0.8 v 1.2 v cmos level ? 0.3 ? vddi 0.3 v operation junction temperature tj ? 40 ?+ 125 c
CS101 series 6 electrical characteristics ? single power supply : vdd = 1.2 v (vdd = 1.2 v 0.1 v, vss = 0 v, tj = ? 40 c to + 125 c) ? dual power supply : vdde = 2.5 v, vddi = 1.2 v (vdde = 2.5 v 0.2 v, vddi = 1.2 v 0.1 v, vss = 0 v, tj = ? 40 c to + 125 c) ? dual power supply : vdde = 3.3 v, vddi = 1.2 v (vdde = 3.3 v 0.3 v, vddi = 1.2 v 0.1 v, vss = 0 v, tj = ? 40 c to + 125 c) * : the input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor is used. parameter symbol conditions value unit min typ max h level output voltage voh ioh = ? 100 avdd ? 0.1 ? vdd v l level output voltage vol iol = 100 a0 ? 0.1 v input leakage current il ???? a pull-up/pull-down resistor rp vil = 0 at pull-up vih = vdd at pull-down ? 12 (target value) ? k ? parameter symbol conditions value unit min typ max h level output voltage voh3 2.5 v output, ioh = ? 100 avdde ? 0.2 ? vdde v voh2 1.2 v output, ioh = ? 100 avddi ? 0.1 ? vddi v l level output voltage vol3 2.5 v output, iol = 100 a0 ? 0.2 v vol2 1.2 v output, iol = 100 a0 ? 0.1 v input leakage current il ???? a pull-up/pull-down resistor rp 2.5 v, vil = 0 at pull-up/ vih = vdde at pull-down ? 25 ? k ? 1.2 v, vil = 0 at pull-up/ vih = vddi at pull-down ? 12 ? k ? parameter symbol conditions value unit min typ max h level output voltage voh3 3.3 v, ioh = ? 100 avdde ? 0.2 ? vdde v voh2 1.2 v, ioh = ? 100 avddi ? 0.1 ? vddi v l level output voltage vol3 3.3 v, iol = 100 a0 ? 0.2 v vol2 1.2 v, iol = 100 a0 ? 0.1 v input leakage current* il ??? 4 a pull-up/pull-down resistor rp 3.3 v, vil = 0 at pull-up/ vih = vdde at pull-down 15 33 70 k ? 1.2 v, vil = 0 at pull-up/ vih = vdde at pull-down ? 12 ? k ?
CS101 series 7 ac characteristics (with low power consump tion, high density CS101sl library used) *1 : delay time = propagation delay time, enable time, disable time *2 : ?typ? is calculated based on the cell specifications. *3 : measurement condition i/o pin capacitance note : the capacitance values vary depending on the package and pin positions. design methods fujitsu?s reference design flow provides the following func tions that help shorten the development time of large scale and high quality lsis. high reliability design estimation in the early stage of physical design realized by physical prototyping. layout synthesis with optimized timing realized by physical synthesis tools. high accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and crosstalk. i/o design environment (power line design, assignment and selection of i/os, package selection) considering noise. packages packages available for existing series can be used fo r CS101 series. this allows smooth replacement with previously developed products. please contact your fujitsu agent for details of delivery times. fbga package : max 424 pins fc-bga package : max 2116 pins pbga package : max 420 pins tebga package : max 900 pins (packages under planning are included.) parameter symbol value unit min typ max delay time tpd * 1 typ * 2 tmin * 3 typ * 2 ttyp * 3 typ * 2 tmax * 3 ns measurement condition tmin ttyp tmax vdd = 1.2 v 0.1 v, vss = 0 v, tj = ? 40 c to + 125 c 0.62 1.00 1.57 parameter symbol value unit input pin cin max16 pf output pin cout max16 pf i/o pin ci/o max16 pf
CS101 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0602 ? 2006 fujitsu limited printed in japan
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